Because of new TDMA (Time Division Multiple Access) and TDD (Time Division Duplex) standards, such as HSCSD, GPRS, WCDMA/TDD and Bluetooth, determining a signal settling time has a key role in wireless communications systems. In said standards, a time window between a TX slot and an RX slot is getting shorter and shorter.
Transceivers in radio-frequency communications systems, such as mobile systems, employ frequency synthesizers for generating a radio-frequency signal. Previous implementations have employed a so-called integer-N synthesizer, in which a feedback divider divides a frequency arriving in a phase detector by an integer N. When the divider input has received N pulses, the output provides one pulse.
The frequency synthesizer 100 of FIG. 1a, such as an integer-N synthesizer, as well as a fractional-N synthesizer to be presented below, comprises a phase lock loop (references 101 to 104) (PLL), i.e. a feedback control system, which further comprises a divider 104 for dividing an output signal frequency of a voltage controlled oscillator 103, a phase detector 101 for generating a control signal to the voltage controlled oscillator 103 in response to a phase difference between a reference signal and the signal coming from the divider 104, a loop filter 102 for filtering said control signal into control voltage, and for providing the output frequency of the voltage controlled oscillator (VCO) 103 on the basis of the received control voltage. The PLL frequency synthesizer also comprises a reference frequency source, which can be e.g. a temperature-compensated crystal oscillator, and a divider 104 control 105 for implementing the division of the VCO frequency.
FIG. 2a shows a simplified phase detector 101 of a frequency synthesizer, i.e. a phase frequency detector (PFD), which phase detector may comprise a D flip-flop 201 for detecting a reference pulse and a second flip-flop for detecting a VCO pulse and a reset means 207, e.g. an AND gate, by means of which the flip-flops 201 and 202 are reset, when an opposite pulse arrives in the phase detector. The phase detector 101 is generally followed by a charge-pump-type current source (203, 204) and a loop filter 102, which may comprise a resistor 205 and a capacitor 206, by which the current pulses generated by the charge pumps are converted to control voltage. PFD compares phase difference between two incoming signals Ref and VCO, and as presented in FIG. 2b provides the output of the flip-flop 201 with an up-pulse U, which controls the charge pump 203 to generate a current pulse IU, when the reference frequency fRef exceeds the compared frequency fVCO. Correspondingly, the output of the flip-flop 202 is provided with a down-pulse D, which controls the charge pump 204 to generate a current pulse ID, when the reference frequency fRef is lower than the compared frequency fVCO. The length of said up- or down-pulse in time is proportional to the phase difference between two incoming signals. The current pulse is integrated to be voltage in the loop filter according to a transfer function F(s) of the loop filter 102. The provided direct voltage VVCO is used for controlling the frequency of a local oscillator. The magnitude of the currents IU and ID is constant during the pulse, but the charge (Q=i*t) integrated in the pulse changes. Because the linear operating range of the phase detector is ±2π, the maximum current pulse width is obtained when the phase difference is 2π. If the incoming phase difference exceeds 2π, the current pulse width changes to its lowest value in a manner presented in FIG. 3a, whereby the phase comparison range becomes non-linear.
A fractional-N synthesizer differs from the integer-N synthesizer in that a frequency arriving in the phase detector 101 is generated on an alternating principle between two different frequencies. In the fractional-N synthesizer, the employed reference frequency is generally higher than in the integer-N synthesizer, because the output frequency resolution can be lower than the reference frequency. A higher reference frequency is an advantageous feature of the synthesizer output in view of interference and noise levels, which, on one hand, allows the use of a large loop band width and thus reduces the synthesizer settling time in a frequency hop. On the other hand, to reduce the noise band width of the phase lock loop and to attenuate a phase comparison frequency the phase-locked loop should have as narrow a band as possible, which enhances the stability of the loop. However, a narrow band delays the loop, which means an increase in the settling time in the frequency synthesizer.
In order to be able to utilize the fractional-N synthesizer technology in an optimal manner as a fast settling synthesizer solution, cycle slips, which result from a typically high phase comparison frequency of the fractional-N synthesizer, are to be avoided. In current solutions cycle slips occur when the phase difference between the signals to be compared exceeds the linear operating range of the phase detector, which operating range in current technology generally is ±2π. FIG. 1b shows signal settling on transferring from frequency f1 to frequency f2, when there is no cycle slip. This situation prevails, when the phase difference between the signals to be compared is less than 2π. However, a high comparision frequency may cause cycle slips, like those presented in FIG. 1c, in the signal settling, particularly in large frequency hops, which further increases the settling time of the frequency synthesizer.
U.S. Pat. No. 6,100,721 discloses a solution for extending the variation range of a phase detector used in connection with a frequency synthesizer, such as an integer-N synthesizer, to exceed the commonly used ±2π. Said publication sets forth a phase detector, which comprises a first pair of D flip-flops for detecting a phase difference between an input frequency and a reference frequency. Said first pair of flip-flops controls two first current sources of a charge pump to generate an error signal, which error signal controls a voltage controlled oscillator to generate an oscillator signal, whose frequency is D times the reference frequency and in which D is typically an integer (e.g. 1,000). The phase detector also comprises a second pair of D flip-flops, which detects when the input frequency is more than 2π ahead of or behind the reference frequency. The second pair of flip-flops is implemented to increase or decrease a counter value, the counter in turn controlling additional current sources of the charge pump. The additional current sources extend the linear operating range of the error signal, when the phase difference exceeds +2π, or correspondingly, is less than −2π. When the phase detector is in state, which corresponds to a phase comparison range of −2π, +2π, only two first current sources form a control signal. When the phase difference exceeds 2π, the counter value is increased, and in response to the increased value an additional current source is turned on, whereby a phase comparison range of 0,4π is proceeded to. Said phase comparison range is maintained until the phase difference between the input frequency and the reference frequency is again zero. Only after the phase difference between the reference signal and the compared signal has reached zero, said additional constant current is switched off, whereby a phase comparison range of −2π,+2π is returned to.